The present invention relates generally to electronic memory, and more specifically to spin transfer torque storage elements that provide improved bit error rate performance.
Electronic memory can be classified as volatile or non-volatile. Volatile memory retains its stored data only when power is supplied to the memory, but non-volatile memory retains its stored data without constant power. Volatile random access memory (RAM) provides fast read/write speeds and easy re-write capability. However, when system power is switched off, any information not copied from volatile RAM to a hard drive is lost. Although non-volatile memory does not require constant power to retain its stored data, it in general has lower read/write speeds and a relatively limited lifetime in comparison to volatile memory.
Magnetoresistive random access memory (MRAM) is a non-volatile memory that combines a magnetic device with standard silicon-based microelectronics to achieve the combined attributes of non-volatility, high-speed read/write operations, high read/write endurance and data retention. The term “magnetoresistance” describes the effect whereby a change to certain magnetic states of the MTJ storage element (or “bit”) results in a change to the MTJ resistance, hence the name “Magnetoresistive” RAM. Data is stored in MRAM as magnetic states or characteristics (e.g., magnetization direction, magnetic polarity, magnetic moment, etc.) instead of electric charges. In a typical configuration, each MRAM cell includes a transistor, a magnetic tunnel junction (MTJ) device for data storage, a bit line and a word line. In general, the MTJ's electrical resistance will be high or low based on the relative magnetic states of certain MTJ layers. Data is written to the MTJ by applying certain magnetic fields or charge currents to switch the magnetic states of certain MTJ layers. Data is read by detecting the resistance of the MTJ. Using a magnetic state/characteristic for storage has two main benefits. First, unlike electric charge, magnetic state does not leak away with time, so the stored data remains even when system power is turned off. Second, switching magnetic states has no known wear-out mechanism.
STT is a phenomenon that can be leveraged in MTJ-based storage elements to assist in switching the storage element from one storage state (e.g., “0” or “1”) to another storage state (e.g., “1” or “0”). For example, STT-MRAM 100 shown in FIG. 1 uses electrons that have been spin-polarized to switch the magnetic state (i.e., the magnetization direction 110) of a free layer 108 of MTJ 102. The MTJ 102 is configured to include a reference/fixed magnetic layer 104, a thin dielectric tunnel barrier 106 and a free magnetic layer 108. The MTJ 102 has a low resistance when the magnetization direction 110 of its free layer 108 is parallel to the magnetization direction 112 of its fixed layer 104. Conversely, the MTJ 102 has a high resistance when its free layer 108 has a magnetization direction 110 that is oriented anti-parallel to the magnetization direction 112 of its fixed layer 104. STT-MRAM 100 includes the multi-layered MTJ 102 in series with the FET 120, which is gated by a word line (WL) 124. The BL 126 is coupled to the MTJ 102, and the SL 128 is coupled to the FET 120. The MTJ 102 (which is one of multiple MTJ storage elements along the BL 126) is selected by turning on its WL 124.
The MTJ 102 can be read by activating its associated word line transistor (e.g., field effect transistor (FET) 120), which switches current from a bit line (BL) 126 through the MTJ 102. The MTJ resistance can be determined from the sensed current, which is itself based on the polarity of the magnetization direction 110 of the free layer 108. Conventionally, if the magnetization directions 112 of the fixed layer 104 and the magnetization 110 of the free layer 108 have the same polarities, the resistance is low and a “0” is read. If the magnetization direction 112 of the fixed layer 104 and the magnetization direction 110 of the free layer 108 have opposite polarities, the resistance is higher and a “1” is read.
When a voltage (e.g., 500 mV) is forced across the MTJ 102 from the BL 126 to the SL 128, current flows through the selected cell's MTJ 102 to write it into a particular state, which is determined by the polarity of the applied voltage (BL high vs. SL high). During the write operation, spin-polarized electrons generated in the reference layer 104 tunnel through the tunnel layer 106 and exert a torque on the free layer 108, which can switch the magnetization direction 110 of the free layer 108. Thus, the amount of current required to write to a STT-MRAM MTJ depends on how efficiently spin polarization is generated in the MTJ. Additionally, STT-MRAM designs that keep write currents small (e.g., Ic<25 micro-ampere) are important to improving STT-MRAM scalability. This is because a larger switching current would require a larger transistor (e.g., FET 120), which would inhibit the ability to scale up STT-MRAM density.
STT-MRAM technologies have been proposed to reduce the switching current by improving or increasing the generation of spin torque electrons. For example, it is more difficult to change the magnetization direction of the MTJ free layer at a normal operating temperature. Accordingly, so-called “thermally-assisted” or “thermoelectric” STT-MRAM has been developed that uses the application of heat to reduce the required switching current. In a known configuration, the thermally-assisted STT-MRAM includes a MTJ and a tunnel junction programming circuit. The MTJ includes a reference layer having a fixed magnetization direction, a tunnel barrier layer, and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The free layer includes a first layer having a first Curie temperature and a second layer having a second Curie temperature different from the first Curie temperature. A material's Cure temperature is the temperatures at which the material becomes nonmagnetic. The tunnel junction programming circuit is configured to apply a current through the MTJ to generate a write temperature in the MTJ and assist in writing (i.e., switching) the magnetization direction of the MTJ free layer.
Another consideration in STT-MRAM is the bit error rate (BER). In digital transmissions, the number of bit errors is the number of data stream bits received over a communication channel that have been altered due to noise, interference, distortion or bit synchronization errors. The BER is defined generally as the number of bit errors per unit time. The basic mechanisms that contribute to the BER of a given STT-MRAM design include thermal disturbance, read disturbance, and probabilistic write failure. The write process of a spin torque MTJ storage element is inherently stochastic due to thermal fluctuations, which give rise to a distribution of the magnetization of the free layer before and during switching. As a result, the time taken by the spin torque MTJ to switch can have a wide distribution. Therefore, there will be a non-zero probability that when a finite duration write pulse is turned off the spin torque MTJ will not have been written, which results in a so-called write error. The probability that a write error takes place for a given applied current pulse of a given length is known as the write error rate (WER). It has been estimated that correct operation of an STT-MRAM array can require that the WER is less than 10−9 if there is an error correction circuit (ECC) in the chip. This means that if 10−9 write pulses are applied, the MTJ reliably writes all but one (1). If there is no ECC, it has been estimated that the WER needs to be less than 10−19.
Returning now to the concept of STT, the spin torque that is applied to the MTJ free layer is proportional to the sine of θ, where θ is the angle between the free layer magnetization direction and the reference layer magnetization direction. In a zero temperature environment, when the STT-MRAM switching process starts, there is no spin torque because θ is equal to zero (0) degrees (i.e., the magnetization directions of the fixed and free layers are parallel) or 180 degrees (i.e., the magnetization directions of the fixed and free layers are anti-parallel), and the sine of zero (0) degrees or 180 degrees is zero (0). In practice, however, there typically exists a very small but finite temperature that fluctuates by very small amounts. The very small fluctuations in temperature oscillate the free layer back and forth by a very small amount. Thus, in practice, the sine θ term at the start of the write process is not precisely zero (0) but is still very small and not sufficient to generate spin torque electrons in the fixed layer. However, in a thermally-assisted STT-MRAM, as the write current raises the MTJ temperature the free layer magnetization direction begins to change, and the sine θ term ramps up to become increasingly larger. After a period of time (e.g., about 1 nanosecond (ns)), the θ term is sufficiently large to generate sufficient spin torque to begin the process of switching the free layer magnetization direction. This spin torque ramp up period, which is inherent to known STT-MRAM configurations results in inherent switching delays that can increase the WER. Accordingly, a contributing factor to WER in thermally-assisted MTJ storage elements is that no or insufficient spin torque is generated at the start of the write operation because sine θ, at the start of a write operation and for a period of time thereafter, is either zero (0) or very close to zero (0).